1. Field of the Invention
The present invention relates to an input protection circuit for use in a semiconductor device, and more specifically to an input protection circuit comprising a protection device configured to absorb an electrostatic noise applied to a semiconductor circuit element by use of a bipolar action, and a protection resistor using a buffering effect based on R.multidot.C time constant of a resistance and a capacitance.
2. Description of Related Art
Referring to FIG. 1, there is shown a diagrammatic section view of an input part of a prior art semiconductor device. In addition, FIG. 2A is a layout pattern diagram of an input protection circuit in the prior art semiconductor device shown in FIG. 1, and FIG. 2B is a sectional view taken along the line X--X in FIG. 2A. FIG. 3 is a circuit diagram of the input part of a prior art semiconductor device shown in FIG. 1.
The prior art input protection circuit designated by Reference Numeral 100 in FIG. 3, comprises an input signal pad 15(IN) selectively coated on an interlayer insulator film 14 formed above a P-type silicon substrate 1, and a first bipolar protection device NPN1 constituted of a first N.sup.+ diffused layer 11 connected through a contact hole CH1 to the input signal pad 15(IN) and formed at a surface portion of the P-type silicon substrate 1, and a second N.sup.+ diffused layer 12 formed at the surface portion of the P-type silicon substrate 1, to extend in parallel to the first N.sup.+ diffused layer 11 but separately from the first N.sup.+ diffused layer 11 by a constant space, for example, 1.6 .mu.m, a P.sup.+ diffused layer 13 formed in the above mentioned space and joined to the first and second N.sup.+ diffused layers 11 and 12 (this P.sup.+ diffused layer 13 being also connected to a channel stopper 4), and a VCC power supply line 15(VCC) connected to the second N.sup.+ diffused layer 12.
The input protection circuit 100 also includes a second bipolar protection device NPN2 which is formed similarly to the first bipolar protection device NPN1 but which is connected to a GND power supply line 15(GND) in place of the VCC power supply line 15(VCC), an input protection resistor R having a pair of N.sup.+ diffused layers 10R selectively formed at a surface portion of opposite ends of a diffused layer 2R, which is formed simultaneously with an N-well 2 (a first terminal, which is composed of one of the pair of N.sup.+ diffused layers 10R, is connected to the input signal pad 15(IN), and a second terminal, which is composed of the other of the pair of N.sup.+ diffused layers 10R, is connected to an input signal internal wiring conductor 15(INA)).
The input protection circuit 100 further includes another protection device (BVds element) composed of a gate electrode 6B coated through a gate oxide film on a surface of the P-type silicon substrate 1, an N.sup.+ drain region 7BD formed selectively on the surface portion of the P-type silicon substrate 1 and connected to the input signal internal wiring conductor 15(INA), and an N.sup.+ source region 7BS formed selectively on the surface portion of the P-type silicon substrate 1 and connected to the gate electrode 6B through a contact hole CH2 and to the GND power supply line 15(GND).
If an electrostatic overvoltage is applied to the input signal pad 15(IN), the bipolar protection device NPN1 or NPN2 exerts a bipolar transistor action to put the input voltage in a negative resistance region, so that the overvoltage is suppressed. Furthermore, a buffering caused by the time constant of a resistance of the input protection resistor R and its wiring capacitance, prevents an abrupt spike from reaching an internal circuit 200. Thus, the electrostatic overvoltage is prevented from being applied to the internal circuit 200.
As mentioned above, the bipolar protection device NPN1 and NPN2 of the prior art input protection circuit have the P.sup.+ diffused layer 13 which is formed, for the purpose of improving the device isolation, between the N.sup.+ diffused layer 11 connected to the input signal pad and the N.sup.+ diffused layer 12 connected to the VCC power supply line or the GND power supply line. When a backward high voltage is applied to the N.sup.+ diffused layer 11, hot carriers are generated in a depletion layer, and a portion of the generated hor carriers is injected into and accumulated in a device isolation oxide film 3. This is a cause for a leakage current.
In addition, since the thickness of the depletion layer of a N.sup.+ P.sup.+ junction is narrow, a relatively high voltage cannot be ultimately applied. For example, under a condition prescribed under MIL-STD-883C, if the voltage applied to the input signal pad exceeds +600V in comparison with the VCC power supply line or the GND power supply line, the leakage current after this positive voltage is applied, becomes 0.1 .mu.A or more.
As mentioned above, the prior art input protection circuit is disadvantageous in that the leakage current is easy to occur.